TSMC to raise wafer foundry prices by 3% to 6% starting next year, order visibility extends to 2030.

BlockBeats news, September 24: TSMC has determined that starting from January 2027, it will adjust wafer output prices by process node, with an overall increase of about 3% to 6%. Among these, advanced processes such as 2nm and 3nm will see the largest increases, while mature and specialty processes will be negotiated separately based on product, utilization rate, and customer conditions.

Currently, TSMC's 8-inch wafer fab capacity utilization rate has exceeded 100%, processes below 45nm are at full load, and visibility for some orders has extended to 2030. The expansion of AI data centers is not only continuously driving demand for GPUs, ASICs, and HBM, but also boosting orders for mature-process chips such as PMICs, MCUs, MOSFETs, and analog ICs.

Supply chain personnel said that capacity for 2nm and 3nm remains persistently in short supply, bottlenecks in advanced packaging capacity such as CoWoS have still not been fully alleviated, and it will be difficult for customers to avoid price increases in the short term by switching suppliers. This price adjustment is also expected to pass through to wafer foundries such as Samsung Electronics, Intel, UMC, and VIS, as well as to segments including packaging and testing and IC design.

Industry insiders pointed out that the growing demand from AI servers for chips used in power management, network communications, and optical communications has caused AI demand to spill over from advanced processes to mature processes, driving a recovery in capacity utilization for mature processes that previously faced relatively weak supply and demand, and strengthening the bargaining power of wafer foundries accordingly.

In addition, the high capital expenditure and cost pressure brought by TSMC's overseas fab construction have also become one of the backgrounds for this price increase. Supply chain personnel expect that wafer foundry price increases in 2027 may further drive up costs in segments such as packaging and testing, substrates, materials, and memory.