TL;DR
· J.P. Morgan's supply chain check raised TSMC's CoWoS forecast, with end-of-2028 monthly capacity expected to reach around 220,000 wafers.
· NVIDIA, AMD, and cloud providers' in-house chip efforts are all pushing for advanced packaging, with a projected 20% supply-demand gap expected from 2027 to 2028.
· Relevant shipment, packaging roadmaps, and customer allocations are mostly model assumptions, with variables such as CoPoS, EMIB-T, and outsourced assembly test yields still in play.

J.P. Morgan's latest supply chain check further raised TSMC's CoWoS production capacity forecast, but its core conclusion is not "the shortage is ending soon" but rather "production capacity is expanding rapidly while demand is running even faster." In the firm's model, the supply-demand gap for advanced packaging from 2027 to 2028 may still remain at around 20%.

This is significant because AI chips cannot be delivered by merely creating a GPU. High-end GPUs, AI CPUs, ASICs, and HBMs need to be placed in the same package for high-speed interconnectivity, with CoWoS being one of the most critical advanced packaging solutions. Companies such as NVIDIA, AMD, Google, Amazon, etc., with AI hardware, often cannot bypass this requirement.

TSMC's official public materials have confirmed the company's continuous expansion of CoWoS, SoIC, and other advanced packaging capacities, stating that CoWoS capacity had a compound annual growth rate of over 80% from 2022 to 2027. However, the specific monthly capacity, customer allocations, yields, and gap ratios for each year have not been disclosed by TSMC, and the market currently relies more on brokerage supply chain checks and third-party estimates.

Why Is Increasing Capacity to Around 220,000 Wafers Not Enough?

In this J.P. Morgan supply chain check, the most direct figure is TSMC's in-house CoWoS monthly capacity forecast: around 115,000 wafers by the end of 2026, around 190,000 wafers by the end of 2027, and around 220,000 to 225,000 wafers by the end of 2028.

There are slight differences in publicly reported second-hand accounts. Some reports suggest that J.P. Morgan's earlier forecast was around 175,000 wafers per month by the end of 2027 and around 220,000 wafers per month by the end of 2028. Considering that these numbers are not officially disclosed by TSMC, it is more appropriate to understand them as "upward revision" scenarios in the supply chain model rather than locked-in capacity commitments.

Outsourced assembly and test (OSAT) companies are also stepping up. The CoWoS-like capacity of OSATs such as Amkor and JCET is expected to increase from around 12,000 to 15,000 wafers per month by the end of 2026 to around 85,000 wafers per month by the end of 2028. TSMC's internal resources are also shifting towards CoWoS, with some capacity originally leaning towards SoIC being redirected to support CoWoS.

CoWoS Capacity Expansion Trend: TSMC's monthly capacity is expected to increase from around 115,000 wafers in 2026 to around 220,000 to 225,000 wafers in 2028, with non-TSMC capacity also being ramped up simultaneously.

However, the issue lies in the increasing packaging consumption of AI chips. High-end AI accelerators, AI CPUs, and custom ASICs are all increasing their packaging requirements, with some chip designs having larger sizes, requiring more wafers and packaging resources per chip. In other words, as production lines expand, the capacity consumed by a single chip is also increasing.

This approximately 20% capacity gap assessment is not the market consensus. TrendForce stated in June that the CoWoS supply-demand gap may narrow from 20% to around 10% by the end of 2026, estimating TSMC's monthly capacity in 2026 to be between 120,000 and 140,000 wafers, with OSAT adding 50,000 to 60,000 wafers per month. The difference between these two assessments mainly stems from varying assumptions on the speed of demand ramp-up and whether external capacity can smoothly translate into available supply.

NVIDIA Remains the Largest Customer, CPUs Also Joining the Queue

According to the JPMorgan model, NVIDIA remains the biggest driver of CoWoS demand. By 2028, NVIDIA's annual CoWoS demand is expected to reach around 1.735 million wafers, showing significant growth compared to 2027.

This demand comes not only from the next-generation GPU but also includes AI CPUs such as Vera, Rosa, LPUs, and products like Spectrum-X CPO. In the model's assumptions, NVIDIA's accelerators and CPO products mainly use CoWoS-L, while CPUs and LPUs rely more on CoWoS-R, shared among TSMC, Amkor, and JCET.

This marks a key shift. Previously, when discussing AI servers, people more easily associated them with "GPU + HBM"; now the CPU side also requires higher memory bandwidth, more complex interconnects, and greater system efficiency. Therefore, AI CPUs themselves will also consume advanced packaging capacity.

The Feynman-related designs are still not entirely certain. The current supply chain model does not explicitly state that it has adopted CoPoS, and in the short term, it is more likely to primarily use CoWoS-L with some SoIC logic stacking. Even if new packaging routes emerge in the future, mainstream AI products from 2027 to 2028 will still find it challenging to bypass CoWoS.

AMD, TPU, and Trainium Join the Fray as Shortage Not Limited to NVIDIA

By focusing solely on NVIDIA, one would underestimate the breadth of the current advanced packaging crunch. AMD, Google TPU, and Amazon Trainium are also increasing their demand for CoWoS or similar advanced packaging.

AMD is under pressure from both ends, the server CPU and AI accelerator. Products such as the Venice server CPU, MI450, and MI500 all require more advanced packaging resources, with MI500 being larger in size and consuming more wafer and packaging capacity per unit. AMD's overall die-level fan-out demand is expected to continue to rise from 2027 to 2028, but the actual fulfillment rate may only be 50% to 60%.

Google TPU is also ramping up. The total shipment forecast for TPUs in 2027 has been raised, with the v8 series involving contributions from MediaTek leading to a significant increase, and the v9 product cycle will also commence in 2028. Some of the subsequent TPU projects may shift to Intel EMIB-T packaging, but this alternative route is still constrained by substrate supply and yield.

Amazon Trainium is likewise accelerating. The lifecycle demand for Trainium3 has been raised, with some orders possibly spilling over to Marvell. Trainium4 is expected to ramp up in 2028, introducing 3D SoIC logic stacking and various interconnect schemes. The related shipment volume and packaging roadmap are still model assumptions, and the ultimate outcome will depend on customer design wins and production pace.

This explains why, despite TSMC's increase in advanced packaging capacity, the market is still concerned about its sufficiency. Demand is no longer solely concentrated on NVIDIA GPUs; instead, it encompasses in-house chips from cloud providers, AI CPUs, and more complex packaging structures, all contributing to the rise in capacity consumption.

Price Target of NT$3100, Betting on Continued Tightness in Packaging

JPMorgan Chase maintains its "Overweight" rating on TSMC and sets a price target of NT$3100 for June 2027, corresponding to approximately 20 times the forward P/E ratio. The institution has simultaneously raised its assumptions for TSMC's data center AI business growth rate, expecting a compound annual growth rate of about 69% from 2024 to 2029.

This price target is supported not only by the increase in CoWoS pricing but also by the combined effect of advanced processes, packaging capacity, and AI customer orders driving up revenue visibility. From 2026 to 2028, TSMC's overall CoWoS consumption is estimated to reach approximately 1.24 million, 2.38 million, and 2.63 million wafers per year, with NVIDIA maintaining the largest share and AMD and Broadcom/TPU contributing more incremental volume.

CoWoS Customer Portfolio Evolution: Total Demand is expected to increase from around 134,000 wafers/year in 2023 to around 2.38 million wafers/year in 2027, with NVIDIA still holding the majority share.

However, these valuation figures are not the most crucial part to zoom in on. A more direct signal is that the expansion of AI infrastructure is pushing TSMC's advanced packaging to a supply bottleneck. For high-end AI chip companies, getting access to advanced process capacity is not enough; whether they can secure an adequate supply of CoWoS may also determine their delivery schedule.

The Alternative Route Has Not Smoothly Sailed, with Variables Still Post-2028

This round of adjustments still has clear boundaries: many figures are based on model assumptions, which do not equate to confirmed outcomes.

CoPoS is still in the engineering validation stage. The current timeline points to risk production in early 2028 and mass production in 2029, but risk production does not mean that customer products will be mass-produced on schedule. Whether NVIDIA's Feynman and other future products will adopt CoPoS remains dependent on final design choices.

Image Note: TSMC's SoIC capacity is expected to ramp up significantly in 2028

OSAT expansion is also not a one-to-one replacement. Outsourced assembly and test (OSAT) companies can take on some CoWoS-like capacity, but substrate yield rates, customer qualifications, equipment readiness, and production priority will all impact the actual availability. Assumptions about AMD and other customers' fulfillment rates are conservative, indicating that external capacity cannot immediately fill the gap.

Intel's EMIB-T is another potential alternative. Third-party estimates suggest that EMIB-T costs may be lower than CoWoS-L, prompting some TPU projects to consider shifting to this route. However, whether the cost advantage can be realized still depends on substrate supply, yield rates, and experience with large-scale production.

Therefore, the true conclusion of this supply chain check is not that "TSMC is ramping up production fast enough," but rather that AI chips are becoming larger, more complex, and more diverse. TSMC and OSAT companies are both accelerating production expansion, but until CoPoS, EMIB-T, and OSAT capacities stabilize and ramp up, advanced packaging could still bottleneck the delivery of high-end AI hardware from 2027 to 2028.

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