TL;DR
· AMAT showcased its DRAM and Advanced Packaging roadmap on June 25, stating that its DRAM equipment share has risen to first place globally.
· Next-generation DRAM, HBM, and Hybrid Bonding require more deposition, etch, and metrology steps, with AMAT covering 15 out of 19 steps in the TSV process.
· Continued share growth still depends on customer capital expenditure, 3D DRAM yield, and panel-level packaging production pace.
Applied Materials, Inc. (AMAT) concentrated on showcasing the AI era's memory and packaging equipment roadmap at the June 25 DRAM and Advanced Packaging Technology Seminar. Deutsche Bank maintained a Buy rating, citing that AI servers are pushing DRAM, HBM, and advanced packaging towards a more complex manufacturing process.
This was not merely a new equipment release. For investors, the key is that the bottleneck of AI servers lies not only in the GPU itself, but in the increasingly challenging manufacturing processes surrounding the GPU, such as high-bandwidth memory, DRAM stacking, chip interconnects, and packaging substrates. The more complex the process, the more steps equipment suppliers can be involved in, potentially shifting capital expenditure from "buying more wafer capacity" to "acquiring more complex materials engineering equipment."
The most direct number provided by AMAT is: its DRAM market share has increased from less than 15% in 2013 to currently hold the global number one position. The company is attempting to demonstrate that AI memory upgrades are not a one-time demand but a systemic transformation encompassing DRAM transistors, interconnects, bonding, packaging, and metrology.
Over the past two years, the market's focus on AI hardware has mostly been on GPUs and advanced processes. However, once truly entering large-scale cluster deployment, memory bandwidth, power consumption, and packaging density have become critical factors limiting overall system performance.
HBM is a prime example. By stacking multiple layers of DRAM, it enhances bandwidth. But as the stack gets higher and the wafers thinner, challenges in manufacturing such as warpage, void fill, alignment, and defect inspection all increase. For equipment suppliers, this means more deposition, etch, clean, polish, bond, and metrology steps entering the addressable market.
What AMAT emphasized this time was not a single-point device but coverage breadth. In the TSV process of HBM packaging, out of 19 material engineering steps, 15 can be covered by its products. TSV is a critical process where vertical vias are punched through the silicon wafer, filled with metal for multilayer interconnects, serving as a key stage when HBM stacking moves to higher levels.
In the new equipment lineup, Avila 2 CVD addresses the warpage issue for thinner HBM DRAM wafers; Nokota VMax 2 is used for void-free filling of smaller TSVs; while OPTA Quad CMP incorporates real-time control into the advanced packaging's chemical mechanical planarization process. These products all point to the same thing: the AI memory upgrade is not about the breakthrough of a single device, but rather multiple process steps simultaneously becoming more challenging.
AMAT summarizes the next-generation DRAM changes into five key directions: EUV patterning, advanced transistor and wiring, CMOS bond pads, 4F² vertical transistor DRAM, and 3D DRAM.
Behind these terms lies the reality that DRAM faces as it continues to shrink and enhance performance. The traditional planar structure is increasingly finding it hard to simultaneously meet density, power, and cost requirements. Memory manufacturers need to introduce more complex patterning, finer interconnects, higher aspect ratio structures, and stacking and bonding methods closer to logic chips.
EUV patterning will increase the demand for high-precision etching; FinFET, copper interconnects, and epitaxial processes will make transistors and wiring more dependent on materials engineering; CMOS bond pads separate the array and peripheral logic for separate manufacturing before bonding; 4F² vertical transistors and 3D DRAM further complicate challenges in high aspect ratio silicon channels, conductor etching, and e-beam metrology.
This is also why AMAT emphasizes the change in its DRAM market share. In 2013, the company's share of the DRAM equipment market was less than 15%, but now claims to have reached the top spot globally. If DRAM shifts from 2D scaling to more 3D and bonded structures, the coverage on deposition, etch, epitaxy, and metrology seen in the past may continue to expand.
However, it would be oversimplified to think that "DRAM technology upgrades equal AMAT's share will inevitably continue to rise." The pace at which memory manufacturers adopt new structures, yield ramp rates, unit capital expenditure constraints, and competitors' responses in etch, deposition, and metrology will all determine actual order placements.
Apart from DRAM itself, advanced packaging is another key focus for AMAT this time.
The need for higher density, lower power interconnects between AI accelerators and HBM is putting pressure on traditional silicon interposer solutions in terms of area and cost. The direction proposed by AMAT is larger-sized panel-level substrates, starting from 310×310mm, 510×515mm, further progressing to 600×600mm.
The larger the panel, the potential benefits include increased single-processing area and reduced packaging costs, but the manufacturing difficulty also significantly increases. Deposition, etching, plating, planarization, and defect control on large-area substrates are all more challenging to maintain consistency. AMAT has laid out digital lithography, panel PVD/CVD/etching, and complemented its large-area copper plating capabilities through the NEXX acquisition.
Of more interest is the Kinex Hybrid Bonding System. It integrates plasma surface activation, cleaning, bonding, and metrology, touted by AMAT as the industry's first integrated dye-to-wafer hybrid bonding system. The value of hybrid bonding lies in making the interconnection between chips denser, shorter, and more power-efficient, suitable for future high-bandwidth memory and logic chip tightly integrated packaging routes.
Around process control, AMAT also introduced VeritySEM 7AP and SEMVision G7AP, used for hybrid bonding solder pads, TSVs, micro-bump critical dimension measurements, and defect review and classification. Advanced packaging has transitioned from "sealing the chip" to "a high-precision process similar to front-end manufacturing," with the importance of metrology and defect detection on the rise.
Deutsche Bank's positive assessment is based on one premise: AI's demand for performance per watt will continue to drive up memory and packaging capital intensity, and AMAT's combination in deposition, etching, CMP, bonding, and metrology is comprehensive enough.
This explains why the market is willing to refocus on semiconductor equipment suppliers like AMAT. If AI investment only remains in GPU procurement, the beneficiary chain is relatively concentrated; but if HBM, DRAM, and advanced packaging all require new processes and equipment, the segments in which equipment suppliers can participate will significantly expand.
However, the risks are equally clear. First, memory customer capital expenditure is cyclical, and strong AI demand does not mean DRAM manufacturers will endlessly expand production. Second, 3D DRAM, 4F² vertical transistors, and hybrid bonding all require yield verification; a lab route does not equate to large-scale production. Third, although panel-level packaging is cost-effective, consistency and defect control on large-size substrates remain industry challenges.
AMAT has transformed itself from a "DRAM equipment market share follower" to a "core equipment platform for AI memory upgrades." What truly supports this narrative next is not the number of product names but how many new processes customers bring into production lines and whether these processes actually bring in more sustainable orders.

AMAT historical recommendation and target price change chart, showing the 2023 to 2026 stock price uptrend and rating adjustment background.
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