Beating AI News Flash: According to an exclusive report by LatePost, Shi Yunfeng, the head of ByteDance's AI chip and DPU team, has submitted his resignation and is currently handing over his work. The AI chip that ByteDance completed tape-out this year did not meet performance expectations and has not yet been deployed at scale in internal businesses; the team is developing the next-generation product.
ByteDance began building an AI chip team in 2019 and chose an ASIC route similar to Google's TPU, hoping to optimize computing efficiency and energy consumption for its own AI businesses. Currently, Ada for Doubao and SeedChip for Seedance are still advancing operator adaptation—that is, enabling the various computational operations in the models to run correctly and efficiently on the self-developed chips—but progress has been limited.
The difficulty of this route lies in the software ecosystem. Nvidia GPUs already have a mature CUDA toolchain, while ByteDance's ASIC needs additional adaptation for models, computing frameworks, and low-level software. Google has invested a massive engineering team in TPU and has long developed supporting tools. ByteDance's business units, however, urgently need more computing power and can hardly spare manpower to repeatedly debug immature chips; directly purchasing mature GPUs is an easier way to meet demand.
ByteDance just adjusted its chip business structure in February this year. Former head Wang Jian no longer oversees chips; the AI chip and DPU team led by Shi Yunfeng and the CPU team led by Yu Hongbin now report directly to Vice President Yang Zhenyuan. Now, Shi Yunfeng, who has led AI chip R&D for many years, has also submitted his resignation.
In addition to internal development, ByteDance has also tried to bring in external chip technology. ByteDance had planned to merge an invested chip project into its self-developed team Picoheart, but the deal has not yet closed.
Another route is cooperation with Xinyuan Semiconductor to develop AI inference chips using the new memory technology ReRAM. Xinyuan's latest sample adopts a multi-chiplet integration design, attempting to integrate more computing power, but manufacturing cost and yield remain unresolved. A person familiar with the matter revealed that, under the current design, the effective dies produced from a single 12-inch wafer are only enough to manufacture about 4 compute cards.
