Huawei Semiconductor Chief Warns: NVIDIA Chip Scale Expansion Approaching Physical Limits, Crossing the Threshold Will Trigger a 'Avalanche'

BlockBeats News, August 4th. In a recent public interview, Dr. Liao Heng, Chief Scientist of Huawei's Semiconductor Business and one of the founding members of the Ascend AI chip, issued a warning. He stated that Western chip giants, led by NVIDIA, are approaching the physical limit in their pursuit of more powerful processors. "There is inevitably a ceiling to scaling by continuously increasing the compute cores and adding more HBM. The industry is still advancing, but once this physical limit is crossed, an avalanche will occur."

Dr. Liao compared the entire AI value chain to an "18-layer tower," in line with NVIDIA CEO Jensen Huang's "layer cake" framework. He emphasized that China needs to establish collaborative capabilities at every layer, particularly stressing the close cooperation between chip manufacturers and AI model developers. Dr. Liao also revealed that Huawei is about to launch its first smartphone chip designed based on the Tau Scaling Law framework, achieved through LogicFolding technology. He mentioned that after organizations such as SemiAnalysis and TechInsights dissect and analyze it, "the world will have a clearer understanding later this year of how this alternative path helps narrow the gap."

The Tau Scaling Law is an innovative design concept proposed by Huawei, focusing on enhancing the transfer speed between various components of a computing system as the inherent advantages of chip miniaturization gradually diminish.

Dr. Liao also highly praised DeepSeek's founder, Wenfeng Liang, believing that the key to training top models with extremely low computing power by 2025 lies in innovative model architecture design. He likened Chinese AI innovation to maximizing space in a small apartment, while Western counterparts live in more spacious villas. Dr. Liao stated that Huawei itself is also developing AI chips that can better support efficient architectures through a chip and model collaborative design mechanism. "We must invest more effort in design to trade higher complexity for less computing resource consumption."