Huawei's "Tao Law" V2 Paper Released: Kirin 2026 Data Revealed for the First Time, Supplementing Engineering Details and Measured Data

According to Omdia monitoring, on July 3, Huawei's semiconductor head, He Tingbo, published the paper "Time Microscaling Theory for Multilevel Electronic Systems" (Tao Law) V2 on the China Science and Technology Paper Preprint Platform ChinaXiv. Compared to the V1 version released on May 25, the new version has supplemented a large amount of engineering implementation details and empirical quantified data based on the theoretical framework, forming an 8-chapter complete exposition system. It has also added principles and physical schematic diagrams covering the τ-level spatiotemporal model, LogicFolding architecture, key bond interface section, Unified Bus interconnect architecture, Hi-ONE optical engine, and other core technologies.

At the engineering implementation level, V2 elaborates deeply on the "Gear Ratio" concept of LogicFolding: when the hybrid bond pitch is close to the top-level metal wiring size, the 3D design space shifts from traditional "macroblock-level discrete optimization" to "unit-level continuous optimization." This enables globally optimal vertical logic partitioning, breaking through the limitation of traditional 3D stacking that can only be layered by functional blocks. V2 also provides production-measured data for the first time, explicitly listing the voltage, frequency, normalized power consumption, area, and power density parameters of Kirin 2026 and the reference Kirin 9030 Pro, further experimentally validating the post-Moore's Law scaling theory centered around the time constant τ.

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