SemiAnalysis: SPHBM4 New Standard Could Alleviate AI Advanced Packaging Bottleneck, Benefiting Substrate Industry

BlockBeats News, July 3, Semiconductor and AI independent research firm SemiAnalysis published an article stating that JEDEC announced the SPHBM4 new standard last week, namely the High Bandwidth Memory standard JESD330-4. SPHBM4 uses the same DRAM stack as HBM4, but switches to a different buffer chip. The goal is to achieve HBM assembly in a standard package and alleviate the AI advanced packaging bottleneck. The concept of SPHBM4 is to maintain the performance of HBM4 while significantly reducing reliance on expensive and supply-constrained advanced packaging.

SPHBM4 is a significant positive development for the substrate industry. On the one hand, traditional HBM must be kept very close to the GPU because the wide parallel signals quickly attenuate with distance. In contrast, SPHBM4 uses high-speed serial channels, allowing the memory to be placed up to 20 mm away. With the expansion of the package size, the total area of substrate material required per chip will increase significantly. On the other hand, direct 32 Gbps signals passing through the organic substrate will increase electrical complexity. SPHBM4 will drive the use of high-end high-density ABF substrates with 20 to 28 layers or more, as well as future glass substrates.

It is indicated that SPHBM4 will shift the AI chip's complex engineering burden from the "silicon interposer + ABF substrate" combination to oversized, high-layer-count ABF substrates, and even accelerate the adoption of glass substrates in advance. "The prosperity of substrates is just beginning."