Huawei has proposed the τ Scaling Law, and the Kirin chip will first utilize LogicFolding this autumn.

According to Observing Beating's monitoring, Huawei unveiled the τ Scaling Law at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS), proposing to use time scaling instead of geometric scaling to seek a new path for the evolution of chips and electronic systems. Based on the time scaling approach, Huawei introduced the LogicFolding architecture and announced that the Kirin chip to be released in the fall of 2026 will be the first to adopt the LogicFolding architecture.

The traditional Moore's Law relies on continuous transistor size reduction, but advanced processes are facing physical limits and diminishing cost benefits. At the core of the τ Scaling Law is the systematic reduction of signal and data propagation time in devices, circuits, chips, and systems, thereby enhancing performance, energy efficiency, and equivalent transistor density.

At the device level, Huawei aims to reduce the time constant τ by optimizing the resistance and parasitic capacitance of transistors and interconnects. At the circuit level, LogicFolding breaks traditional circuit layout boundaries, shortens critical path routing, and reduces the resistive-capacitive load of signal propagation. At the chip level, Huawei enhances parallel efficiency through software, architecture, and chip co-design. At the system level, the UnifiedBus interconnect protocol is geared towards SuperPoD to achieve unified memory addressing and native memory semantics, reducing system communication latency.

Huawei stated that over the past 6 years, they have designed and mass-produced 381 chips based on the τ Scaling Law, covering scenarios such as smartphones and AI computing. The company expects that by 2031, high-end chips designed based on the τ Scaling Law will reach 14 Å, equivalent to a 1.4 nm process transistor density. Huawei has currently disclosed the design methodology and route goals and has not provided independent performance test data for LogicFolding on the Kirin chip.