BlockBeats News, August 19th, Citrini analyst Jukan cited a report from the South Korean media that Samsung Electronics plans to adjust the design of the ongoing Pyeongtaek P5 wafer fab, upgrading the original two-story building to a three-story structure.
This adjustment involves the Pyeongtaek P5 Fab 1 and Fab 2, with both fabs set to jointly form the world's largest single-site semiconductor manufacturing base. The project started construction in 2022 and is expected to be completed by 2030, with a peak construction period seeing about 50,000 workers involved.
Previously, Samsung's Pyeongtaek campus P4 and earlier fabs have adopted a "twin-wafer fab" layout, with each building containing 4 clean rooms. If the P5 three-story design is approved, it will employ a "triple-wafer fab" structure, accommodating up to 6 clean rooms.
Under this plan, the number of clean rooms in P5 is expected to increase by about 50%, and the overall production capacity is also expected to increase by at least 50%. In the future, Samsung Electronics and SK Hynix may also adopt similar three-story wafer fab designs for new wafer fabs in the Pyeongtaek Semiconductor Industrial Complex.
Industry insiders believe that Samsung's expansion of its advanced manufacturing base reflects the accelerating demand for global AI chips, with storage and advanced process capacity expansion picking up pace.

