Google has been reported to partner with AMD to design the next-generation TPU, with CPU core IP playing a key role, indicating that the future of AI may rely more on CPU-intensive computing.

BlockBeats News, August 17th, according to a SemiAnalysis customer report citing market sources, Google is collaborating with AMD to develop a product in the 10th-generation TPU. This will be AMD's first truly involvement in a custom AI ASIC project. Analysts believe that Google has nine generations of TPU development experience and has long been responsible for actual silicon design by Broadcom. Traditional TPU design does not require AMD, so the core attraction of the collaboration lies in AMD's CPU IP, advanced packaging, and interconnect technology.

The report specifically points out that Google and its customers are driving the integration of CPU cores within the TPU package to address the needs of CPU-intensive workloads such as reinforcement learning. While traditional LLM training remains accelerator-centric, inference and agent-based reinforcement learning require more general compute resources to run around the accelerator.

This trend has been evident in Google's recent hardware configuration. The TPU 8i system, designed for inference, reasoning, and reinforcement learning workloads, pairs one Google Axion CPU with every two TPUs; whereas the 7th-generation TPU servers only pair one Intel Xeon processor with every four TPUs. There are reports suggesting that in some scenarios, a 1:1 ratio of CPU to accelerator is the optimal solution, implying that the future of AI computing may rely far more on CPUs than the current market perception. If the collaboration with AMD becomes a reality, Google will integrate its proprietary TPU accelerator with AMD's general-purpose computing cores to create a hybrid AI ASIC, which may reshape the competitive landscape of data center chips.