TSMC is building a Production Line Pilot (PLP) system to significantly improve the efficiency of AI chip production

BlockBeats News, June 15th, according to etnews, TSMC will adopt the next-generation semiconductor packaging technology "Panel Level Packaging (PLP)" to compete head-to-head with Samsung Electronics. PLP can significantly improve the production efficiency of AI chips, and as TSMC accelerates its mass production preparation, the battle for leadership between it and Samsung Electronics, which was the first to enter this market, seems inevitable.

According to industry sources on the 15th, TSMC is building the Material, Components, and Equipment (MCE) supply chain to establish its PLP mass production system. Currently, TSMC is in discussions with domestic and foreign MCE companies regarding equipment investment. It is reported that TSMC plans to start PLP mass production as early as next year, a move seen as a substantial step towards this objective.

PLP is a technology that cuts the finished circuit-manufactured wafer into individual chips (dies), and then packages them on a rectangular panel to produce the final product. It is contrasted with "Wafer Level Packaging (WLP)" carried out on circular wafers. When chips are packaged on circular wafers, the edge area cannot be made into chips and must be discarded—resulting in lower productivity. Packaging on rectangular panels, however, enables chip production without any waste. Calculated on a standard 600×600 mm rectangular panel, it can produce approximately five to six times the number of chips compared to mainstream 300 mm (12-inch) wafers.

Currently, Samsung Electronics holds the advantage in PLP technology. After acquiring the PLP business from Samsung Electro-Mechanics in 2019, Samsung Electronics continuously accumulated its technological capabilities by applying this technology to mobile application processors (AP) and power management ICs (PMIC).

In contrast, TSMC has been relatively passive in PLP technology before, as it has established a competitive advantage in the foundry field with its traditional Wafer Level Packaging (WLP). However, with the explosive growth of the AI chip market, the situation has reversed—PLP can increase the output of AI chips and is conducive to realizing large-area AI chips. Therefore, TSMC has been actively promoting its PLP business since 2024. TSMC is expected to complete and operate a pilot production line this year, and after performance evaluation, enter mass production around next year. It is reported that TSMC has already secured a global AI chip customer.

As TSMC accelerates the mass production of PLP, the competition with Samsung Electronics is expected to intensify further. Samsung also plans to expand the application of PLP from existing APs and PMICs to High-Performance Computing (HPC) chips, such as AI semiconductors. Additionally, the glass substrate, which is highly anticipated as the substrate for AI chips, is also likely to be applied in this PLP process—indicating that Samsung Electronics and TSMC will also engage in a battle for leadership in the next-generation substrate market.

An industry insider stated, "Not only Samsung Electronics and TSMC, but also global Outsourced Semiconductor Assembly and Test (OSAT) companies have significantly entered the PLP technology market," and added, "Intense competition is expected, and the market is poised for growth."